present invention relates to an improved output circuit operated by an internal power source. More particularly, it relates to measures to protect an output circuit having an output terminal connected to an external signal line when a signal higher in voltage than the above internal power source is applied by other circuit to the above external signal line.
With the increasing miniaturization of LSIs, the thickness of an oxide film used therein has been reduced in recent years. Accordingly, operation only with a voltage of 3.3 V or less is ensured to the latest LSIs fabricated using submicron design rules, while conventional LSIs fabricated using 1 .mu.m design rules are operable with a voltage of 5 V. In the case of using the latest LSI operable with a voltage of 3.3 V, therefore, there should be no problem if all the external LSIs are of the latest type (items operable with 3.3 V). However, the following problem arises if the external LSIs are conventional ones operable with a voltage of 5 V (items operable with 5 V). Specifically, if an external signal line is connected to each of a 3.3 V I/O pin of an output circuit provided in the latest LSI and to a 5 V I/O pin of an output circuit provided in any conventional LSI, a voltage of 5 V from the above external signal line is applied to the 3.3 V I/O pin of the output circuit of the latest LSI, since the potential of the external signal line has been set to 5 V by the output circuit of the conventional LSI. As a result, a current flows into the output circuit of the latest LSI operable with 3.3 V through the 3.3 V I/O pin and a voltage of 5 V is applied to an oxide film, which leads to the problem that normal operation cannot be ensured to the latest LSI.
To overcome the problem, a circuit as shown in FIG. 3(a) has conventionally been proposed as a 3 V/5 V interface I/O circuit with which normal operation of the latest LSI is ensured.
Below, a description will be given to the conventional output circuit shown in FIG. 3(a). In the drawing is shown a bonding pad 601 as an output terminal, to which is connected an external signal line (not shown). To the external signal line is applied a signal having a higher voltage (e.g., 5 V) than an on-chip (internal) power-source voltage VDD (e.g., 3.3 V) by other output circuit.
In the drawing are also shown: a P-channel (hereinafter referred to as P-ch) output transistor 602 for supplying the internal power-source voltage VDD to the above pad 601; an N-channel (hereinafter referred to as N-ch) output transistor for connecting the above pad 601 to the ground; an input signal IN; a control signal C which brings the above output circuit into an output state when the potential thereof is LOW and into a high impedance state when the potential thereof is HIGH; and an inverter 611.
In the drawing are further shown: an NAND circuit 609 which produces a LOW output if the control signal C is LOW and the input signal IN is HIGH, thereby turning ON the above P-ch output transistor 602 and bringing the pad 601 into a HIGH output state; and an NOR circuit 610 which produces a HIGH output if the control signal C is LOW and the input signal IN is LOW, thereby turning ON the above N-ch output transistor 604 and bringing the pad 601 into a LOW output state.
The output circuit of FIG. 3(a) is obtained by adding to the above basic structure the following components, which are: N-ch transistors 603 and 607; and P-ch transistors 605, 606, and 608 using a substrate in common to which no power-source voltage VDD has been applied. In the drawing, the mark * designates a substrate potential different from the on-chip power-source voltage VDD. The P-ch transistor 606 has its drain connected to the substrate.
Next, a description will be given to the operation of the above output circuit of FIG. 3(a).
If a voltage of 5 V is applied from the external signal line to the bonding pad 601 with its output being in the high impedance state, a current is allowed to flow from the drain of the P-ch transistor 602 to its substrate through the PN junction thereof, thereby raising the potential of the substrate. After the potential of the substrate became 5 V, the above current flowing through the PN junction does not flow any longer. Since the internal power-source voltage VDD (3.3 V) has been applied to the gate of the P-ch transistor 605, the P-ch transistor 605 is in the ON state with respect to 5 V. Consequently, a current is allowed to flow from the bonding pad 601 to the gate of the P-ch output transistor 602 via the P-ch transistor 605. After the potential of the P-ch output transistor 602 became 5 V, the drain current from the P-ch transistor 605 does not flow any longer. Moreover, since the P-ch output transistor 602 is turned OFF when the potential of the gate of the P-ch output transistor 602 became 5 V, a current from the bonding pad 601 to the internal power source VDD does not flow any longer. Since the internal power-source voltage VDD has been applied to the gate of the N-ch transistor 607, the N-ch transistor 607 remains in the OFF state even if the potential of the drain of the N-ch transistor 607 is 5 V, so that the potential of 5 V is not transmitted to the output of the NAND circuit 609. As for the P-ch transistor 608, since the respective potentials of the gate and drain thereof are 5 V, the P-ch transistor 608 also remains in the OFF state, so that the potential of 5 V is not transmitted to the output of the NAND circuit 609, either. The P-ch transistor 606 is provided for the purpose of returning, when the potential of the bonding pad 601 shifted to the LOW level, the potential of the N-WELL designated by the mark * to the power-source voltage VDD (3.3 V).
Thus, the potentials at the gate, drain, and source of each of the P-ch transistors 602, 605, 606, and 608 and N-ch transistor 607 are either the internal power-source voltage VDD (3.3 V) or 5 V. Hence, there is no possibility that a voltage equal to or higher than the breakdown voltage of a gate oxide film of each of the transistors is constantly applied to the gate oxide film, so that normal operation of the output circuit with 3.3 V is ensured.
However, as a result of close examination of the operation of the above circuit, the present inventors have found the drawback that, even in the above structure, a voltage equal to or higher than the breakdown voltage may be transiently placed on an oxide film of a transistor when a transition is made from the high impedance state to the output state, from the-output state to the high impedance state, or from the output state to the input state.
In other words, the present inventors have found the drawback that, as diagrammatically shown in FIG. 3(b) and as can be appreciated from the result of simulation by a transistor simulator SPICE shown in FIG. 3(c), the voltage between the gate and source of the P-ch transistor 608 may be equal to or higher than the breakdown voltage of the oxide film of the P-ch 608 and placed thereon when the bonding pad 601 makes a transition from the high impedance state of 5 V to the output state of 3 V.
The foregoing drawback is not limited to a transient period during which the output state is shifting, as described above. The drawback also arises when, e.g., the predetermined timing was not provided in the HIGH output state and the voltage of 5 V is applied. The above drawback is also observed in an output circuit the structure of which is not limited to that shown in FIG. 3(a).